PhD candidate - Computer Science - Yale University

Quantum Error Correction and multi-FPGA architectures

ආයුබෝවන්...

AYUBOWAN... (Wish you a long life)

I am a PhD candidate in the Computer Science Department at Yale University, advised by Professor Lin Zhong at the Yale Efficient Computing Lab. My research focuses on building scalable multi-FPGA systems for quantum error correction (QEC) and control.

In 2023, I co-developed Helios, a scalable surface code decoder. Helios was the first design to achieve a decreasing average time per measurement round as code distance increases. It also became the first decoder to support real-time decoding for surface codes of distance up to 51. The Distributed Union-Find algorithm used in Helios has since been adopted by commercial QEC platforms.

In 2025, we introduced DecoNet, the first network-integrated decoding system that scales compute and I/O resources by trivially adding FPGA nodes. DecoNet decodes 100 logical qubits with lattice surgery in real time using five interconnected FPGAs. To our knowledge, it is the first system to demonstrate real-time decoding of 100 interacting logical qubits under lattice surgery.

I began my graduate studies at Rice University, earning an MSc in Electrical and Computer Engineering in 2020, before transferring to Yale to pursue my PhD. I interned at Google (Sunnyvale) in 2019 and previously worked at Paraqum Technologies, where I developed FPGA-based video encoders for the HEVC standard.

Contact : namitha.liyanage@yale.edu

Office : 309 Arthur K. Watson Hall

Profiles : LinkedIn | Google Scholar| Github

Recent Updates

Our work DecoNet is now available in arxiv (PDF)
Our paper Micro-Blossom is accepted for ASPLOS 2025
'Present a poster on LEGO: QEC Decoding System Architecture for Dynamic Circuits at Quantum OS workshop 2024.
Panelist on "Real-Time Decoders for Quantum Error Correction" at IEEE QCE 2024
Presented our work on the first multi-FPGA-based surface code decoder at IEEE QCE 2024
Presented our poster titled "Multi-FPGA system for quantum error correction with lattice surgery" at IEEE QCE 2024
Our paper on distributed Union-Find Decoder has been accepted in IEEE Transactions on Quantum Engineering
Our latest work on FPGA implementation for a distributed Union-Find decoder is now available in arxiv (PDF)
Gave an invited talk at the Kobe Quantum Error Correction Symposium in January 2024
Presented our paper titled "Scalable Quantum Error Correction for Surface Codes using FPGA" at QCE 2023 (PDF)
Francesco Battistel presented our work in the Error Correction workshop at QCE 2023.
Spend the summer at Qblox, Netherlands working on implementing our distributed Error decoder inside Qblox stack.
Present a poster on FPGA-based Quantum Error decoders at FCCM 2023.
Our latest work on distributed UF decoder is now available in the arxiv (PDF)

Research

Multi-FPGA system for quantum error correction

Highlights :

First multi-FPGA-based QEC decoder,
First scalable decoder implementation that can decode dynamic decoder graphs

A practical decoder for quantum error correction must decode a dynamic decoding graph comprising all logical qubits in the system in real time, a challenging task due to resource limitations. Helios-net, a first-of-its-kind decoding system that overcomes resource constraints through a distributed multi-FPGA architecture. It employs a hybrid tree-grid topology to minimize latency for lattice surgery operations distributed across multiple FPGAs. Furthermore, Helios-net introduces fusion-Union-Find, a novel approach to decoding merged logical qubits that avoids redundant computations associated with traditional window decoders. Additionally, we designed Helios-net architecture to overcome the IO limitation and minimize data movement latency when integrating with existing quantum control systems. Our exploratory prototype of \name consists of five Xilinx VMK-180 FPGAs and can decode 100 logical qubits (d=5) faster than the rate of measurement.

FPGA-based Distributed UF Decoder for Surface Codes

Relevant papers

FPGA-based Distributed Union-Find Decoder for Surface Codes (Accepted for IEEE TQE)
Scalable Quantum Error Correction for Surface Codes using FPGA (IEEE QCE 2023)

Highlights

First decoder to scale to arbitrary large code distances due to decreasing decoding time per measurement round with increasing d
First decoder to decode d up to 21 in real-time. (Can support up to d=51)
Introduced distributed UF algorithm (adopted by Riverlane for commercial production)

A fault-tolerant quantum computer must decode and correct errors faster than they appear to prevent exponential slowdown due to error correction. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than O(d^3). We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to d, given $O(d^3)$ parallel computing resources. The decoding time per measurement round decreases as d increases, the first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using a Xilinx VCU129 FPGA, we successfully implement d up to 21 with an average decoding time of 11.5 ns per measurement round under 0.1% phenomenological noise, and 23.7 ns for d=17 under equivalent circuit-level noise. This performance is significantly faster than any existing decoder implementation. Furthermore, we show that \name can optimize for resource efficiency by decoding d=51 on a Xilinx VCU129 FPGA with an average latency of 544ns per measurement round.

For my past projects : Click Here

Education

2020 - : Yale University

PhD candidate in Computer Science

Master of Science in Computer Science (2022)

Master of Philosophy in Computer Science (2023)

2017 - 2020 : Rice University

Master of Science in Electrical and Computer Engineering

2010 - 2015 : University of Moratuwa

Bachelor of the Science in Electronic and Telecommunication Engineering

(Rank 2 out of 100 students)

Professional Experience

FPGA engineering Intern (2023) at Qblox

Implemented a distributed union find decoder inside Qblox stack

Software Engineering Intern (2019) at Google

Worked on FPGA-based application acceleration

Associate Architect (2017 ), Electronic Engineer (2015 - 2017) at ParaQum Technologies (Pvt.) Ltd

Led a team of engineers that designed and developed a real-time all-intra HD HEVC encoder on FPGA
Worked on developing a 4K real-time FPGA-based HEVC decoder to support higher profiles
Worked on developing FPGA-based HEVC - Screen content coding encoder

Application Engineer (Consultancy basis) (2015 - 2017) at Wave Computing

Mapped machine learning algorithms to wave data-flow architecture (novel coarse-grained reconfigurable architecture) using in-house programming tools

Trainee Associate Electronic Engineer (2013-2014) at Zone 24x7 (Pvt.) Ltd

Designed handwriting pre-processing software to be integrated with a computer vision-based check processing library and a computer vision-based information extraction library. This work was judged as the best industrial training project in the Electronics and Telecommunication Category by the Institution of Engineers Sri Lanka for the year 2014

Publications

Namitha Liyanage, Yue Wu, Emmet Houghton and Lin Zhong, "Multi-FPGA system for quantum error correction with lattice surgery" in IEEE Quantum Computing and Engineering (QCE), September 2024

Namitha Liyanage, Yue Wu, Siona Tagare and Lin Zhong, "FPGA-based Distributed Union-Find Decoder for Surface Codes" arXiv preprint arxiv:2406.08491, March 2024 (PDF), (Accepted for IEEE Transactions on Quantum Engineering, September 2024)

Namitha Liyanage, Yue Wu, Alexander Deters and Lin Zhong, "Scalable Quantum Error Correction for Surface Codes using FPGA", in IEEE Quantum Computing and Engineering (QCE), September 2023 (PDF)

Yue Wu, Namitha Liyanage and Lin Zhong, "An interpretation of Union-Find Decoder on Weighted Graphs", arXiv preprint arxiv:2211.03288, November 2022. (PDF)

Kevin Boos, Namitha Liyanage, Ramla Ijaz, and Lin Zhong, "Theseus: an experiment in operating system structure and state management," in Proc. USENIX Symposium on Operating Systems Design and Implementation (OSDI), November 2020. (Source code, PDF)

Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P.M.K. Tharaka, Geethan Karunaratne, R.M.A.U. Senarath, Ishantha Perera, Ashen Ekanayake and Ajith Pasqual, "High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension" in 'The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors' (ASAP), July 2017 (PDF)

Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera and Ajith Pasqual, "Real Time All Intra HEVC HD Encoder on FPGA" in 'The 27th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors' (ASAP), July 2016 (PDF)

Teaching

Teaching Fellow for Technology, Power, and Security: Political Challenges of the Computer Age (CPSC 310) : Yale University 2023

Teaching Fellow for Building Distributed Systems (CPSC 426/526) : Yale University : 2022

Teaching Fellow for Computer System Design (CPSC 429/529) : Yale University : 2021

Grader for Mobile and Embedded Systems (ECE 424/524) : Rice University 2018

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Namitha Liyanage