Namitha  Liyanage

PhD candidate   -  Computer Science  -  Yale University

Quantum Error Correction and multi-FPGA architectures

ආයුබෝවන්...

AYUBOWAN... (Wish you a long life)

I am a PhD candidate in the Computer Science Department at Yale University, working under Professor Lin Zhong at the Yale Efficient Computing Lab. My research centers on developing scalable multi-FPGA systems for Quantum Error Correction and control.


In 2023, our team developed Helios, a scalable surface code decoder. Helios is notable for being the first design with a decreasing average time per measurement round as code distance increases. It was also the first decoder capable of real-time decoding for code distances of up to 51. Riverlane adopted our decoder algorithm for their implementation. Currently, we are working on scaling Helios to operate across multiple FPGAs.


I began my graduate studies at Rice University, where I earned an MSc in Electrical and Computer Engineering in 2020, before moving to Yale in the fall of the same year to continue my research. I interned at Google, Sunnyvale, in the summer of 2019, and prior to graduate school, I worked for two years at Paraqum Technologies, where I developed FPGA-based video encoders for the HEVC standard.


Contact :  namitha.liyanage@yale.edu

Office :  309 Arthur K. Watson Hall

Profiles : LinkedIn | Google Scholar| Github

Recent Updates

Research

Multi-FPGA system for quantum error correction

Highlights : 

A practical decoder for quantum error correction must decode a dynamic decoding graph comprising all logical qubits in the system in real time, a challenging task due to resource limitations. Helios-net, a first-of-its-kind decoding system that overcomes resource constraints through a distributed multi-FPGA architecture. It employs a hybrid tree-grid topology to minimize latency for lattice surgery operations distributed across multiple FPGAs. Furthermore, Helios-net introduces fusion-Union-Find, a novel approach to decoding merged logical qubits that avoids redundant computations associated with traditional window decoders. Additionally, we designed Helios-net architecture to overcome the IO limitation and minimize data movement latency when integrating with existing quantum control systems. Our exploratory prototype of \name consists of five Xilinx VMK-180 FPGAs and can decode 100 logical qubits (d=5) faster than the rate of measurement. 


FPGA-based Distributed UF Decoder for Surface Codes

Relevant papers

FPGA-based Distributed Union-Find Decoder for Surface Codes (Accepted for IEEE TQE)
Scalable Quantum Error Correction for Surface Codes using FPGA (IEEE QCE 2023)

Highlights


A fault-tolerant quantum computer must decode and correct errors faster than they appear to prevent exponential slowdown due to error correction. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than O(d^3). We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to d,  given $O(d^3)$ parallel computing resources. The decoding time per measurement round decreases as d increases, the first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using a Xilinx VCU129 FPGA, we successfully implement d up to 21 with an average decoding time of 11.5 ns per measurement round under 0.1% phenomenological noise, and 23.7 ns for d=17 under equivalent circuit-level noise. This performance is significantly faster than any existing decoder implementation. Furthermore, we show that \name can optimize for resource efficiency by decoding d=51 on a Xilinx VCU129 FPGA with an average latency of 544ns per measurement round.

For my past projects : Click Here

Education

2020 -  : Yale University

PhD candidate in Computer Science

Master of Science in Computer Science (2022)

Master of Philosophy in Computer Science (2023)

2017 - 2020 : Rice University

Master of Science in Electrical and Computer Engineering

2010 - 2015 : University of Moratuwa

Bachelor of the Science in Electronic and Telecommunication Engineering

(Rank 2 out of 100 students)

Professional Experience

FPGA engineering Intern (2023) at Qblox


Software Engineering Intern (2019) at Google


Associate Architect (2017 ), Electronic Engineer (2015 - 2017) at ParaQum Technologies (Pvt.) Ltd


Application Engineer (Consultancy basis) (2015 - 2017) at Wave Computing


Trainee Associate Electronic Engineer (2013-2014) at Zone 24x7 (Pvt.) Ltd

Publications







Teaching